1. Field of the Invention
The present invention relates to a semiconductor device used in a variety of electronic equipment and a method of manufacturing the same and, more particularly, to a technique associated with an alignment or element isolation method thereof.
2. Related Background Art
FIG. 1 is a sectional view of a semiconductor device used in a conventional LSI or the like. More specifically, FIG. 1 shows a typical npn bipolar transistor. A semiconductor substrate 101 consists of a p-type semiconductor. An n.sup.+ -type buried layer 102 and element isolation layers 103 and 103' are formed in the semiconductor substrate 101. A collector contact n.sup.+ -type layer 104 is formed adjacent to the n.sup.+ -type buried layer 102. Field oxide films 105, 105', and 105" can be formed by selective oxidation. An n.sup.- -type epitaxial layer 106 has a thickness of 1.2 to 2 .mu.m and a concentration of about 10.sup.15 cm.sup.-3. The bipolar transistor has a base diffusion layer 107 and an n.sup.+ -type emitter layer 108. In this conventional example, the n.sup.+ -type emitter layer 108 is formed by diffusion from an n.sup.+ -type poly-Si layer 110. An insulating interlayer 109 consists of BPSG (borophosphosilicate glass). Emitter, base, and collector wiring layers 111, 112, and 114 consist of Al--Si. The transistor also has a base contact p.sup.+ -type diffusion layer 113. A passivation film 115 consists of SiN.
Typical parameters for determining the performance of the bipolar transistor having the above structure are a base width W.sub.B and a collector width W.sub.C shown in FIG. 1. It is important to control these widths precisely, to make them as small as possible.
The base width W.sub.B is determined by a method of forming the base diffusion layer 107 and the n.sup.+ -type emitter layer 108 by a low-temperature process and reducing the width of the base diffusion layer 107, a method of reducing the thicknesses of the base and emitter layers, or the like. The base width W.sub.B can be reduced as small as 500 to 1,000 .ANG. on the research and development level.
On the other hand, the collector width W.sub.C cannot be easily reduced for the following reasons.
(Reason 1)
The collector width W.sub.C is defined as the distance between the n.sup.+ -type buried layer 102 and the bottom of the base region having width W.sub.B, i.e., the width of a lightly doped layer subjected to depletion. Unlike the emitter and base regions, the lightly doped layer is located deep in the substrate, and relatively far from the substrate surface.
(Reason 2)
The structures of the n.sup.+ -type buried layer and the like formed in the first half of the process depend on subsequent annealing due to reason 1, and sufficient process margins must be maintained.
(Reason 3)
Impurity layers having different conductivity types must be simultaneously formed inside the substrate from the substrate surface in such a manner that npn and pnp transistors must be formed as bipolar transistors, and NMOS and PMOS transistors must be formed as MOSFETs (the collector width in a BJT corresponds to the width between the gate and the less heavily doped well in a MOSFET). Therefore, the process design is difficult.
A desired collector width cannot be easily realized, due to the above reasons.
In order to solve the above problem, there is attempted a method of forming a buried layer such as the n.sup.+ -type buried layer 102 by high-energy ion implantation. During the ion implantation, however, high-energy ions bombard the side wall of the ion-implantation apparatus and thus produce metal ions, and these ions are also implanted inside the Si substrate, thereby forming crystal defects and degrading the element characteristics and hence posing another technical problem which is more difficult to solve.
In addition, the element isolation region of the conventional semiconductor device should be noticed. Element isolation is performed by the thick field oxide films 105, 105', and 105" and the P-type element isolation layers 103 and 103' thereunder in FIG. 1. Although the field oxide film 105 is preferably formed deep to achieve perfect dielectric isolation, lateral oxidation may cause the insulating layer to occupy most of the surface, and the area of the active region for element formation is thus undesirably reduced.
According to still another technical problem of the prior art, even in a device having a bipolar transistor and a MOS transistor, an element isolation region has a predetermined relationship between its depth and its lateral width. This element isolation region is insufficient to perform effective element layout.
The present inventors carefully examined the fundamental cause for these conventional technical problems, and found that the cause was based on the fact that a semiconductor element was conventionally formed substantially from only one surface of a semiconductor substrate.
More specifically, a semiconductor layer and an insulating layer are formed in one surface of the semiconductor substrate, and etching is also performed from this one surface. The operations on the other surface are limited to electrode formation and deposition of phosphorus glass for extrinsic gettering. All the semiconductor regions and the element isolation regions are selectively formed from the above one surface.
On the other hand, an SOI (Silicon On Insulator) device comprising a substrate with an insulating surface and a semiconductor layer in which an element is formed is known as a device capable of reducing the parasitic capacitance of a semiconductor function element, and capable of performing a high-speed operation. Even in this SOI device, since a semiconductor layer having a thickness of several .mu.m is mainly used, the process is performed from one surface, as a matter of course.
In the design of a semiconductor element, physical values associated with impurity diffusion from the upper surface are used as parameters to determine a base width, an emitter width, a collector width, a channel width, the area of an element isolation region, and the like.
Within the limits of elements formed by this design rule, easily feasible improvements of element characteristics are limited.